1. Field
Example embodiments relate to a tunnel insulation layer structure, a method of manufacturing a tunnel insulation layer structure, and a vertical memory device including a tunnel insulation layer structure. More particularly, example embodiments relate to a vertical memory device having a vertical channel and including the tunnel insulation layer structure.
2. Description of the Related Art
In methods of manufacturing vertical memory devices, an insulation layer and a sacrificial layer may be alternately and repeatedly formed on a substrate. Holes may be formed through the insulation layers and the sacrificial layers. Channels may be formed to fill the holes. Openings may be formed through the insulation layers and the sacrificial layers. The sacrificial layers exposed by the openings may be removed to form gaps exposing the channels. Tunnel insulation layer structures and gate structures including gate electrodes may be formed to fill the gaps.
In this case, a tunnel insulation layer may be disposed between a charge storage layer and the channel. An electrical characteristic of the tunnel insulation layer may be important for determining a performance of the vertical memory device. When a thickness or an equivalent oxide thickness (EOT) of the tunnel insulation layer is large, a program/erase operation of the vertical memory device may be slow. While, when a thickness or an equivalent oxide thickness (EOT) of the tunnel insulation layer is small, a retention characteristic of the vertical memory device may be degraded. Therefore, a vertical memory device having an improved reliability has been studied.